1. Field of the Invention
This invention relates generally to integrated circuit packages, and more particularly to a method of making a leadless ceramic package having improved solderability characteristics.
2. Related Art
In the electronics industry, integrated circuits are commonly encased in packages made of plastic or ceramic. A ceramic integrated circuit package, sometimes referred to as a "chip carrier", comprises a ceramic substrate including electrical contacts to connect an integrated circuit enclosed within the package to external circuitry. The package is hermetically sealed with a lid, which may be, for example, metal or ceramic.
Prior-art methods of fabricating ceramic integrated circuit packages generally process the packages in array form. A package array may be defined as consisting of a plurality of attached individual ceramic package substrates. Conductive traces of a base metal (such as molybdenum-manganese or tungsten) are printed onto the array and into holes formed within the array, and the array is co-fired. At least one set of holes defines the perimeter of each device package. After firing, the array is immersed in an electrolytic bath and the conductive traces are plated with one or more plating metals. After the electroplating has been completed, singulation is performed to cut the array into a plurality of individual device packages.
It is important to note that presently-existing methods of fabricating ceramic packages generally electroplate the packages before singulation takes place. Singulation is generally performed as a final step in the production process. Since the carriers are processed as an array until the final production steps are completed, this method is relatively efficient. However, this production method has major problems related to the solderability of the final product. Solderability is an important parameter; the final product must possess at least a minimum degree of solderability in order to fulfill its intended purpose.
A frequently-cited solderability standard is specified in MIL Standard 883C, Method 2003.6. However, in many cases, this specification must be waived or relaxed, because meeting the specification would entail expensive, impractical rework of the device packages. Presently-existing methods of fabricating chip carriers are not able to consistently meet MIL-STD 883C specifications.
The poor solderability of prior-art packaging methods is attributable to two major causes. First of all, the singulation (snapping) process results in the exposure of base metallization at the perimeter of each package defined by a hole pattern in the pre-singulation array. After singulation, half-cylinders form along these holes, which are referred to as "castellation". The singulation process may also expose the ceramic substrate. Neither the base metal nor the ceramic substrate provides adequate solderability. The base metal is chosen for its adhesion properties to ceramic and not for its desirable solderability characteristics. Consequently, a widely-utilized base metal is either molybdenum-manganese (Mo-Mn) or tungsten (W), both of which have relatively poor solderability. Secondly, the electroplating is performed on the package array. The flow of the electroplating solution is often restricted at the package holes, due to the fact that the holes are of a relatively small diameter (typically 0.010 to 0.020 diameter). Therefore, the plating on the base metal castellations is often of uneven thickness, and some areas may remain unplated.
FIG. 1 is an enlarged perspective view of a typical castellation produced by prior-art package fabrication methods. The package consists of three ceramic layers 40, 42, and 44. The axis of the half-cylinder castellation is along the line 18--18'. Due to the fact that the package arrays are singulated (cut into individual device packages) after plating, the inner coating of base metal 20, 22 is necessarily exposed at the edges of the castellation, along the singulation line. Furthermore, the plating metal is frequently unable to completely penetrate the pre-singulation castellation hole 18, thus resulting in uneven or thin metal plating as shown at 24.
It is therefore desirable to provide a means for fabricating ceramic packages with improved solderability compared to the prior art. The present invention provides such a means.